What Is The Minimum Number Of Clock Cycles Needed To Load A 16-bit Register

Reckoner organization and architecture miscellaneous

The micro-instructions stored in the command retentivity of a processor take a width of 26 flake. Each micro-instruction is divided into three fields; a micro-operation field of 13 chip, a next address field (X), and a MUX select field (Y), there are 8 status bits in the inputs of the MUX.

How many $.25 are there in the Ten and Y fields, and what in the size of the command retentiveness in number of words?

1. x, 3, 1024
2. 8, 5, 256
3. 5, 8, 2048
4. 10, 3, 512

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MUX has viii states bits as input lines and then we require 3 select inputs to select & input lines. No. of $.25 in control memory next address field = 26 – thirteen – 3
= ten
ten scrap addressing, we have 210 memory size. So X, Y size = 10,3,1024
Hence (a) is right option.

Correct Option: A

MUX has viii states bits equally input lines so nosotros require iii select inputs to select & input lines. No. of bits in control memory next address field = 26 – 13 – three
= ten
10 bit addressing, we have 210 retention size. So X, Y size = 10,3,1024
Hence (a) is correct selection.

Consider the post-obit data path of a uncomplicated non-pipelined CPU. The registers A, B, A₁, A_ii, MDR, the passenger vehicle and the ALU are 8-bit wide, SP and MAR are sixteen - bit registers. The MUX is of size 8 × (2: 1) and the DEMUX is of size 8 × (1: two). Each memory functioning takes 2 CPU clock cycles and uses MAR (Memory Address Register) and MDR (Memory Date Register). SP can be decremented locally.

The CPU pedagogy " Push r", where = A or B, has the specification
Grand [SP] ← r
SP ← SP – 1
How many CPU clock cycles are needed to execute the "push r" education?

1. 2
2. 3
3. 4
4. v

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Button 'r'
Consist of post-obit operations
Chiliad [SP] !r
SP! SP – ane
'r' is stored at retentiveness at address stack pointer currently is, this take 2 clock cycles.
SP is then decremented to bespeak to next acme of stack. Then total cycles = 3
Hence (b) is correct selection.

Correct Option: B

Push 'r'
Consist of following operations
Yard [SP] !r
SP! SP – 1
'r' is stored at retentivity at address stack pointer currently is, this take 2 clock cycles.
SP is then decremented to point to side by side top of stack. Then total cycles = 3
Hence (b) is correct option.

Consider the ALU shown beneath :
If the operands are in two's complement representation, which of the following operations can exist performed past suitably setting the control lines Grand and C₀ merely (+ and – denote addition and subtraction respectively)?

1. A + B and A – B but not A + i
2. A + B and A + i merely not A – B
3. A + B but not A – B or A + 1
4. A + B and A – B and A + 1

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Example I :- If k = 1, that means output of EX-OR gate is in complemented class. If add together 1 (by setting CO = i) to this complemented grade then it becomes 2S complement of B. at present adding A to the 2'S complement of B is nothing only subtraction.
Example II :- If k = 0, EX-OR Simply return B. Add A to B without setting co i.e, K = 0,
C 0 = 0, return improver of A and B ⇒ (A+ B)
Example Iii :- We cannot increment A value without changing B content So A + 1 is not possible with given condition. Hence choice (A) is right.

Right Option: A

Case I :- If k = 1, that means output of EX-OR gate is in complemented course. If add 1 (by setting CO = 1) to this complemented form and so information technology becomes 2S complement of B. at present adding A to the 2'S complement of B is nothing but subtraction.
Case Ii :- If k = 0, EX-OR Simply return B. Add A to B without setting co i.e, K = 0,
C 0 = 0, render addition of A and B ⇒ (A+ B)
Case III :- Nosotros cannot increment A value without changing B content So A + 1 is not possible with given condition. Hence option (A) is correct.

Direction: Consider the following data path of a CPU :

The ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to exist carried out in the ALU. Ii clock cycles are needed for memory bus into the MDR.

The instruction "CALL R_n, sub" is a two discussion didactics. Bold that PC is incremented during the fetch bike of the first word of the instruction, its annals transfer interpretation is R_n < = PC + 1 PC < = M [PC]
The minimum number of CPU clock cycles needed during the execution wheel of this pedagogy is

1. 2
2. iii
3. iv
4. five

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The minimum number of CPU clock cycles needed during the execution cycle = iv As 1 cycle required to transfer already incremented value of PC and ii cycle for getting data in MDR1 to load value of MDR in PC.

Correct Option: B

The minimum number of CPU clock cycles needed during the execution cycle = 4 As 1 cycle required to transfer already incremented value of PC and 2 cycle for getting data in MDR1 to load value of MDR in PC.

The instruction "Add together R₀, R_i " has the annals transfer interpretation R₀ < = R₀ + R_ane. The minimum number of clock cycles needed for execution cycle of this educational activity is

1. ii
2. three
3. 4
4. 5

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Given that R₀ ← R₀ + R₁ The clock cycles operate as follows :

Bike 1	Out : R₁
	In : Due south
Cycle 2	Out : R₂
	In : T
Bike 3	Out : Due south, T
	Add : ALU
	In : R

Therefore, execution bicycle is completed in 3 clock cycles.

Correct Option: B

Given that R₀ ← R₀ + R_one The clock cycles operate every bit follows :

Wheel 1	Out : R₁
	In : South
Wheel ii	Out : R₂
	In : T
Cycle three	Out : S, T
	Add together : ALU
	In : R

Therefore, execution cycle is completed in 3 clock cycles.